By Sam Sangani
As gate oxide thickness and dimensions of scale shrink in integrated circuit design, reliability problems occur and need to be considered early in the design process. Some of the more problematic issues include negative bias temperature instability (NBTI) and hot carrier injection (HCI). NBTI is a critical factor in PMOS devices and leads to current degradation, yield loss, and functional failure of integrated circuits. HCI has primarily affected NMOS devices, but today it is also a concern for PMOS devices. HCI is caused by hot carriers in the gate oxide that lead to oxide damages, which manifest themselves as current degradation, Vt shift, leakage current increase, etc.
Over time, both NBTI and HCI degrade device currents and will cause failures in integrated circuits. Circuit designers need to consider these reliability effects in the early stages of design to make sure there are enough margins for circuits to function correctly over their entire lifetime.
HCI and NBTI introduce a threshold voltage increase for the MOS. This may be a real issue for mixed signal applications. There is also a gm transconductance variation. This characteristic changes the gain of transistors, which may not be expected by analog designers.
With HCI and NBTI circuit simulation, designers can detect and locate potential issues. Because HCI is dependent of the horizontal electrical field in the channel, designers can improve the robustness of the devices by increasing their length. There is also an exponential decrease in hot carriers with a decrease in supply voltage. Designers can change the bias conditions of the devices where the issue is found.
NBTI problems are more difficult to fix. Designers can check voltage overshoot to avoid the damage caused by NBTI. They may decide to increase capacitive loads, increase the transconductances, or reduce the supply voltage of the function to reduce NBTI susceptibility.
Designers should make it a priority to study the IO blocks of their designs. Creating robust HCI/NBTI circuits is a new challenge for digital/analog designers.
Designers must need to know to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs.